Over the past decade, packaging becomes increasingly important for microelectronic devices. As the density of semiconductor devices is increasing, the requirement of compactness and reduced-cost for packaging is more demanding. Several new packaging approaches have been proposed to achieve above objects. For examples, a very fine quad flatpack (VFQFP) technology has been developed to improve I/O density and provide very fine pitch QTPs and solder ball grid array.
Another technology competing with the VFQFP is the solder ball grid array (BGA) technology. A plurality of solder balls or solder columns are arranged between ceramic package and the PCB. The solder ball can achieve the function of electrical connection and accommodating the thermal stress due to the TCE mismatch therebetween.
FIG. 1 shows the flowchart of conventional ceramic BGA packaging process. First, the ceramic base of a single-unit form is subjected to polishing. The semiconductor die is then mounted on and adhered to the single-united ceramic base by adhesive paste such as silver epoxy. The mounted die is then subjected to a curing process and a wire-bonding process. Afterward, a transparent lid is covered the resultant structure for providing hermeticity. The sealed package is then subjected a testing process for rejecting those packages unsatisfactory.
However, the above-mentioned process has several problems. The cost is hard to reduce because the high cost of ceramic base. Moreover, the process is begun with a ceramic base of single-united form, and the successive processes need to carry out for each independent ceramic base. This is impedimental to the batch manufacture and laborious. Moreover, there are many processes involving a high temperature step, the die is liable to be damaged and the yield will be accordingly reduced.